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a
5-Bit Programmable Synchronous Controller for Pentium(R) III Processors ADP3157
FUNCTIONAL BLOCK DIAGRAM
VCC DRIVE1 DRIVE2 PGND AGND PWRGD SENSE+ SENSE- DELAY NONOVERLAP DRIVE VREF +15% 2R CROWBAR IN CMPI Q S R gm VREF REFERENCE 1.20V VID0 SENSE- VID1 VID2 R VT1 VREF +5% VREF -5%
FEATURES Active Voltage Positioning with Gain and Offset Adjustment Optimal Compensation for Superior Load Transient Response VRM 8.2, VRM 8.3 and VRM 8.4 Compliant 5-Bit Digitally Programmable 1.3 V to 3.5 V Output Dual N-Channel Synchronous Driver Total Output Accuracy 1% Over Temperature High Efficiency, Current-Mode Operation Short Circuit Protection Overvoltage Protection Crowbar Protects Microprocessors with No Additional External Components Power Good Output SO-16 Package APPLICATIONS Desktop PC Power Supplies for: Pentium II and Pentium III Processor Families AMD-K6 Processors VRM Modules GENERAL DESCRIPTION
SD
VT2
CT
CMPT OFF-TIME CONTROL
ADP3157
DAC
VID3 VID4
The ADP3157 is a highly efficient synchronous buck switching regulator controller optimized for converting the 5 V main supply into the core supply voltage required by the Pentium III and other high performance processors. The ADP3157 uses an internal 5-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 1.3 V and 3.5 V. The ADP3157 uses a current mode, constant off-time architecture to drive two external Nchannel MOSFETs at a programmable switching frequency that can be optimized for size and efficiency. It also uses a unique supplemental regulation technique called active voltage positioning to enhance load transient performance. Active voltage positioning results in a dc/dc converter that meets the stringent output voltage specifications for Pentium II and Pentium III processors, with the minimum number of output capacitors and smallest footprint. Unlike voltage-mode and standard current-mode architectures, active voltage positioning adjusts the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3157 provides accurate and reliable short circuit protection and adjustable current limiting. It also includes an integrated overvoltage crowbar function to protect the microprocessor from destruction in case the core supply exceeds the nominal programmed voltage by more than 15%.
Pentium is a registered trademark of Intel Corporation. All other trademarks are the property of their respective holders.
CMP
VCC +12V 22 F 1F
VIN +5V CIN +
VCC DRIVE1 SD L RSENSE + 1nF SENSE- CT AGND DRIVE2
R1
ADP3157
SENSE+ CMP
VO 1.3V TO 3.5V CO
R2
CCOMP 150pF
PGND VID0-VID4
5-BIT CODE
Figure 1. 5-Bit Code Typical Application
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
ADP3157-SPECIFICATIONS (0 C T +70 C, V
A
CC
= 12 V, VIN = 5 V, unless otherwise noted)1
Min 1.283 1.980 3.465 Typ 1.3 2.0 3.5 0.05 4.1 140 125 145 5.5 250 165 0.6 2.0 Max 1.317 2.020 3.535 Units V V V % mA A mV V V A k A A s ns % % s 24 % k mmho V V kHz 0.6 2.0 10 V V A
Parameter OUTPUT ACCURACY 1.3 V Output Voltage 2.0 V Output Voltage 3.5 V Output Voltage OUTPUT VOLTAGE LINE REGULATION INPUT DC SUPPLY CURRENT Normal Mode Shutdown
2
Symbol VO
Conditions (Figure 13)
VO
ILOAD = 10 A (Figure 2) VIN = 4.75 V to 5.25 V VSD = 0.6 V TA = +25C, VID Pins Floating VSENSE- Forced to VOUT - 3%
IQ
CURRENT SENSE THRESHOLD VOLTAGE VID0-VID4 THRESHOLD Low High VID0-VID4 INPUT CURRENT VID0-VID4 PULL-UP RESISTANCE CT PIN DISCHARGE CURRENT
VSENSE(TH) VID(TH)
IVID RVID I12
VID = 0 V 20 TA = +25C VOUT in Regulation VOUT = 0 V CT = 150 pF CL = 7000 pF (Drive 1, 2) TA = +25C % Above Output Voltage % Below Output Voltage -8 1.8
110 30 65 2 2.45 120 5 -5 500
220
10 3.2 200 8
OFF-TIME DRIVER OUTPUT TRANSITION TIME POSITIVE POWER GOOD TRIP POINT
3 3
tOFF t R , tF VPWRGD VPWRGD tPWRGD VCROWBAR ROERR gm(ERR) VCMPMIN VCMPMAX BWERR SDL SDH SDIC
NEGATIVE POWER GOOD TRIP POINT POWER GOOD RESPONSE TIME CROWBAR TRIP POINT ERROR AMPLIFIER OUTPUT IMPEDANCE ERROR AMPLIFIER TRANSCONDUCTANCE ERROR AMPLIFIER MINIMUM OUTPUT VOLTAGE ERROR AMPLIFIER MAXIMUM OUTPUT VOLTAGE
% Above Output Voltage
9
15 275 2.2
VSENSE+ Forced to VOUT + 3% VSENSE+ Forced to VOUT - 3% CMP = Open Part Active Part in Shutdown
0.8 2.4 500
ERROR AMPLIFIER BANDWIDTH -3 dB SHUTDOWN (SD) PIN Low Threshold High Threshold Input Current
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Dynamic supply current is higher due to the gate change being delivered to the external MOSFETs. 3 The trip point is for the output voltage coming into regulation. Specifications subject to change without notice.
-2-
REV. A
ADP3157
PIN FUNCTION DESCRIPTIONS
Pin No. 1-4, 16
Mnemonic VID1-VID4, VID0 AGND SD SENSE- SENSE+ CT CMP PWRGD VCC DRIVE2 DRIVE1 PGND
Function Voltage Identification DAC Inputs. These pins are pulled up to an internal reference, providing a logic one if left open. The DAC output programs the SENSE- regulation voltage from 1.3 V to 3.5 V. Leaving all five DAC inputs open results in placing the ADP3157 into shutdown. Analog Ground. All internal signals of the ADP3157 are reference to this ground. Shutdown. A logic high will place the ADP3157 in shutdown and disable both outputs. This pin is internally pulled down. Connects to the internal resistor divider that senses the output voltage. This pin is also the (-) input for the current comparator. The (+) input for the current comparator. The output current is sensed as a voltage at this pin with respect to SENSE-. External capacitor CT connection to ground sets the off time of the device. Error Amplifier output and compensation point. The voltage at this output programs the output current control level between the SENSE pins. Power Good. An open drain signal indicates that the output voltage is within a 5% regulation band. Supply Voltage to ADP3157. Gate Drive for the (bottom) synchronous rectifier N-channel MOSFET. The voltage at DRIVE2 swings from ground to VCC. Gate Drive for the buck switch N-channel MOSFET. The voltage at DRIVE1 swings from ground to VCC. Power Ground. The drivers turn off the buck and synchronous MOSFETs by discharging their gate capacitances to this pin. PGND should have a low impedance path to the source of the synchronous MOSFET.
PIN CONFIGURATION
VID1 1 VID2 2 VID3 3 VID4 4
16 15 14
5 6 7 8 9 10 11 12 13 14 15
ABSOLUTE MAXIMUM RATINGS*
Input Supply Voltage (VCC) . . . . . . . . . . . . . . -0.3 V to +16 V VID0-VID4, SD, PWRGD, CMP, CT . . . . . . . -0.3 V to VCC DRIVE1, DRIVE2, SENSE+, SENSE- . . . . . . -0.3 V to VCC Operating Ambient Temperature Range . . . . . . 0C to +70C Junction Temperature Range . . . . . . . . . . . . . . 0C to +150C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110C/W Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged.
VID0 PGND DRIVE1
DRIVE2 TOP VIEW AGND 5 (Not to Scale) 12 VCC
13
ADP3157
SD 6 SENSE- 7 SENSE+
8
11 10 9
PWRGD CMP CT
ORDERING GUIDE
Model ADP3157JR
Temperature Range 0C to +70C
Package Description
Package Options
16-Lead SOIC R-16A/SO-16
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3157 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-3-
ADP3157
22 100k ESR = 25m EACH 2200 F 3 (25V) 22 F L2 1H VIN +5V 1F 1F IRL3803 L1 1.7 H RSENSE 5m ESR = 25m EACH 2200 F 6 (25V) +5V RTN +12V RTN VCC +12V
ADP3157
P SYSTEM
1 2 3 4 5 6 7 8
VID1 VID2 VID3 VID4 AGND SD SENSE- SENSE+
VID0 16 PGND 15 DRIVE1 14 DRIVE2 13 VCC 12 PWRGD 11 CMP 10 CT 9 CT 200pF R2 18.2k R1 105k
IRL3803 10BQ015
VO 1.3V TO 3.5V 0-19A
RTN CCOMP 3600pF
220 220
1nF
Figure 2. Typical VRM8.2/8.3/8.4 Compliant Core DC/DC Converter Circuit
VCC DRIVE1 DRIVE2 PGND
12 14 13
AGND
5
PWRGD
11
SENSE+ SENSE-
DELAY VREF +15% NONOVERLAP DRIVE SD 6 IN CROWBAR 2R
ADP3157
REFERENCE
1.20V VREF +5% CMPI Q S R CMPT VT1 gm VREF R OFF-TIME CONTROL SENSE- DAC
10 4 1
VREF -5% VID0 VID1 VID2 VID3 VID4
VT2
2
CT
3
CMP
Figure 3. Functional Block Diagram
-4-
REV. A
Typical Performance Characteristics- ADP3157
100 VOUT = 3.5V 95 90
EFFICIENCY - %
450 VOUT = 2.8V 400 350
FREQUENCY - kHz
45 40
SUPPLY CURRENT - mA
35 30 25 20 15 10 5 0 45 58 83 134 OPERATING FREQUENCY - kHz 397 QGATE(TOTAL) = 100nC
300 250 200 150 100
85 VOUT = 2.0V 80 75 70 SEE FIGURE 2 65 1.4 2.8 4.2 5.6 7 8.4 9.8 11.2 12.6 14 OUTPUT CURRENT - Amps VOUT = 1.3V
50 0 50 100 200 300 400 500 600 700 800 TIMING CAPACITOR - pF
Figure 4. Efficiency vs. Output Current
Figure 5. Frequency vs. Timing Capacitor
Figure 6. Supply Current vs. Operating Frequency
SEE FIGURE 2
SEE FIGURE 2
PRIMARY N-DRIVE DRIVER OUTPUT
1
VCC = +12V VIN = +5V I OUT = 10A
OUTPUT VOLTAGE 20mV/DIV
SECONDARY N-DRIVE DRIVER OUTPUT
2
OUTPUT CURRENT 19A TO 1A
DRIVE 1 AND 2 = 5V/DIV
500ns/DIV
100ns/DIV
10 s/DIV
Figure 7. Gate Switching Waveforms
Figure 8. Driver Transition Waveforms
Figure 9. Load Transient Response, 19 A-1 A of Figure 2 Circuit
25 TA = +25 C SEE FIGURE 13 20
OUTPUT VOLTAGE 20mV/DIV
VCC VOLTAGE 5V/DIV
NUMBER OF PARTS
15
3
10
OUTPUT CURRENT 1A TO 19A
4
REGULATOR OUTPUT VOLTAGE 1V/DIV
5
10 s/DIV
10ms/DIV
Figure 10. Load Transient Response, 1 A-19 A of Figure 2 Circuit
Figure 11. Power-On Start-Up Waveform
Figure 12. Output Accuracy Distribution, VOUT = 2.0 V
REV. A
-5-
-0.55 -0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
0
OUTPUT ACCURACY - %
ADP3157
Table I. Output Voltage vs. VID Code
12V SD CMP 1k CT 4700pF AGND PGND VOUT VCC 1F 0.1 F
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VOUT 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 No CPU--Shutdown 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50
ADP3157
DRIVE1 DRIVE2 SENSE+ SENSE-
100k 1.2V
OP27
0.1 F
Figure 13. Closed-Loop Test Circuit for Accuracy
THEORY OF OPERATION
The ADP3157 uses a current-mode, constant-off-time control technique to switch a pair of external N-channel MOSFETs in a synchronous buck topology. Constant off-time operation offers several performance advantages, including that no slope compensation is required for stable operation. A unique feature of the constant-off-time control technique is that since the off-time is fixed, the converter's switching frequency is a function of the ratio of input voltage to output voltage. The fixed off-time is programmed by the value of an external capacitor connected to the CT pin. The on-time varies in such a way that a regulated output voltage is maintained as described below in the cycle-bycycle operation. Under fixed operating conditions the on-time does not vary, and it only varies slightly as a function of load. This means that switching frequency is fairly constant in standard VRM applications. In order to maintain a ripple current in the inductor that is independent of the output voltage (which also helps control losses and simplify the inductor design), the off-time is made proportional to the value of the output voltage. Normally, the output voltage is constant and therefore the offtime is constant as well.
Active Voltage Positioning
Cycle-by-Cycle Operation
The output voltage is sensed at the SENSE- pin. A voltage-error amplifier, (gm), amplifies the difference between the output voltage and a programmable reference voltage. The reference voltage is programmed to between 1.3 V and 3.5 V by an internal 5-bit DAC, which reads the code at the voltage identification (VID) pins. Refer to Table I for output voltage vs. VID pin code information. A unique supplemental regulation technique called active voltage positioning with optimal compensation adjusts the output voltage as a function of the load current so that it is always optimally positioned for a load transient. Standard (passive) load voltage positioning, sometimes recommended for use with other architectures, has poor dynamic performance which renders it ineffective under the stringent repetitive transient conditions specified in Intel VRM documents. Consequently, such techniques do not allow the minimum possible number of output capacitors to be used. Optimally compensated active voltage positioning as used in the ADP3157 provides a bandwidth for transient response that is limited only by parasitic output inductance. This yields optimal load transient response with the minimum number of output capacitors.
During normal operation (when the output voltage is regulated), the voltage-error amplifier and the current comparator (CMPI) are the main control elements. (See the block diagram of Figure 3.) During the on-time of the high side MOSFET, CMPI monitors the voltage between the SENSE+ and SENSE- pins. When the voltage level between the two pins reaches the threshold level VT1, the high side drive output is switched to ground, which turns off the high side MOSFET. The timing capacitor CT is then discharged at a rate determined by the off-time controller. While the timing capacitor is discharging, the low side drive output goes high, turning on the low side MOSFET. When the voltage level on the timing capacitor has discharged to the threshold voltage level VT2, comparator CMPT resets the SR flip-flop. The output of the flip-flop forces the low side drive output to go low and the high side drive output to go high. As a result, the low side switch is turned off and the high side switch is turned on. The sequence is then repeated. As the load current increases, the output voltage starts to decrease. This causes an increase in the output of the voltage-error amplifier, which, in turn, leads to an increase in the current comparator threshold VT1, thus tracking the load current. To prevent cross conduction of the external MOSFETs, feedback is incorporated to sense the state of the driver output pins. Before the low side drive output can go high, the high side drive output must be low. Likewise, the high side drive output is unable to go high while the low side drive output is high. -6- REV. A
ADP3157
Power Good
The ADP3157 has an internal monitor that senses the output voltage and drives the PWRGD pin of the device. This pin is an open drain output whose high level (when connected to a pullup resistor) indicates that the output voltage has been within a 5% regulation band of the targeted value for more than 500 s. The PWRGD pin will go low if the output is outside the regulation band for more than 500 s.
Output Crowbar
C T is discharged by a constant current of 65 A. Once CT reaches 2.3 V, a new on-time cycle is initiated. The value of the off-time is calculated using the continuous-mode operating frequency. Assuming a nominal operating frequency of fNOM = 200 kHz at an output voltage of 2.0 V, the corresponding off time is:
V 1 tOFF = 1 - O = 3.0 s VIN f NOM
The timing capacitor can be calculated from the equation:
CT = tOFF x 65 A = 200 pF 1V
An added feature of using an N-channel MOSFET as the synchronous switch is the ability to crowbar the output with the same MOSFET. If the output voltage is 15% greater than the targeted value, the ADP3157 will turn on the lower MOSFET, which will current-limit the source power supply or blow its fuse, pull down the output voltage, and thus save the microprocessor from destruction. The crowbar function releases at approximately 50% of the nominal output voltage. For example, if the output is programmed to 2.0 V, but is pulled up to 2.3 V or above, the crowbar will turn on the lower MOSFET. If in this case the output is pulled down to less than 1.0 V, the crowbar will release, allowing the output voltage to recover to 2.0 V if the fault condition has been removed.
Shutdown
The converter operates at the nominal operating frequency only at the above specified VOUT and at light load. At higher VOUT or heavy load, the operating frequency decreases due to the parasitic voltage drops across the power devices. The actual minimum frequency at VOUT = 2.0 V is calculated to be 180 kHz (see Equation 1), where: IIN RIN RDS(ON)HSF RDS(ON)LSF RSENSE RL is the input dc current (assuming an efficiency of 90%, IIN = 7.5 A) is the resistance of the input filter (estimated value: 7 m) is the resistance of the high side MOSFET (estimated value: 10 m) is the resistance of the low side MOSFET (estimated value: 10 m) is the resistance of the sense resistor (estimated value: 5 m) is the resistance of the inductor (estimated value: 6 m)
The ADP3157 has a shutdown (SD) pin that is pulled down by an internal resistor. In this condition the device functions normally. This pin should be pulled high to disable the output drives.
APPLICATION INFORMATION Specifications for a Design Example
The design parameters for a typical 550 MHz Pentium III application (Figure 2) are as follows: Input voltage: VIN = 5 V Auxiliary input: VCC = 12 V Output voltage: VO = 2.0 V Maximum output current: IOMAX = 17.0 A dc Minimum output current: IOMIN = 1.0 A dc Static tolerance of the supply voltage for the processor core: VOST+ = +70 mV VOST- = -70 mV Transient tolerance (for less than 2 s) of the supply voltage for the processor core when the load changes between the minimum and maximum values with a di/dt of 30 A/s: VOTR+ = +140 mV VOTR- = -140 mV Input current di/dt when the load changes between the minimum and maximum values: less than 8 A/s The above requirements correspond to Intel's published power supply requirements based on Intel Pentium III specifications. CT Selection for Operating Frequency The ADP3157 uses a constant-off-time architecture with tOFF determined by an external timing capacitor CT. Each time the high side N-channel MOSFET switch turns on, the voltage across CT is reset to approximately 3.3 V. During the off time, f MIN = REV. A 1 tOFF x
COUT Selection-Determining the ESR
The required ESR and capacitance drive the selection of the type and quantity of the output capacitors. The ESR must be small enough that both the resistive voltage deviation due to a step change in the load current and the output ripple voltage stay below the values defined in the specification of the supplied microprocessor. The capacitance must be large enough that the output is held up while the inductor current ramps up or down to the value corresponding to the new load current. The total static tolerance of the Pentium III processor is 140 mV. Taking into account the 1% setpoint accuracy of the ADP3157, and assuming a 0.5% (or 10 mV) peak-to-peak ripple, the allowed static voltage deviation of the output voltage when the load changes between the minimum and maximum values is 90 mV. Assuming a step change of I = IOMAX-IOMIN = 16 A, and allocating all of the total allowed static deviation to the contribution of the ESR sets the following limit: 90 mV RE ( MAX ) = ESRMAX1 = = 5.6 m 16 A The output filter capacitor must have an ESR of less than 5.6 m. One can use, for example, two SP-Type OS-CON capacitors from Sanyo, with 2200 F capacitance, 7 V voltage rating, and
VIN - I IN RIN - IOMAX ( RDS(ON )HSF + RSENSE + RL ) - VO = 180 kHz VIN - I IN RIN - IOMAX ( RDS(ON )HSF + RSENSE + RL - RDS(ON )LSF ) -7-
(1)
ADP3157
10 m ESR. The two capacitors have a total ESR of 5.0 m when connected in parallel, which gives adequate margin.
Inductor Selection
Once RSENSE has been chosen, the peak short-circuit current ISC(PK) can be predicted from the following equation: ISC(PK) = (145 mV)/RSENSE = (145 mV)/(5.0 m) = 29 A The actual short-circuit current is less than the above calculated ISC(PK) value because the off-time rapidly increases when the output voltage drops below 1 V. The relationship between the off-time and the output voltage is:
tOFF CT x 1V VO + 2 A 360 k
The minimum inductor value can be calculated from ESR, offtime, dc output voltage and allowed peak-to-peak ripple voltage using the following equation: L MIN1 = VOtOFF RE ( MAX ) 2.0 V x 3 s x 5.3 m = = 3.2 H VRIPPLE, p - p 10 mV
The minimum inductance gives a peak-to-peak ripple current of 2.55 A, or 15% of the maximum dc output current IOMAX. The inductor peak current in normal operation is: ILPEAK = IOMAX + IRPP/2 = 19.5 A The inductor valley current is: ILVALLEY = ILPEAK - IRPP = 14.5 A The inductor for this application should have an inductance of 3.3 H at full load current and should not saturate at the worst-case overload or short circuit current at the maximum specified ambient temperature.
Tips for Selecting the Inductor Core
With a short circuit across the output, the off-time will be about 70 s. During that time the inductor current gradually decays. The amount of decay depends on the L/R time constant in the output circuit. With an inductance of 3.3 H and total resistance of 22 m, the time constant will be 73 s. This yields an average short-circuit current of about 20 A. To safely carry the short-circuit current, the sense resistor must have a power rating of at least 20 A2 x 5.0 m = 2.0 W.
Current Transformer Option
Ferrite designs have very low core loss, so the design should focus on copper loss and on preventing saturation. Molypermalloy, or MPP, is a low loss core material for toroids, and it yields the smallest size inductor, but MPP cores are more expensive than ferrite cores or the Kool M(R) cores from Magnetics, Inc.
COUT Selection-Determining the Capacitance
The minimum capacitance of the output capacitor is determined from the requirement that the output be held up while the inductor current ramps up (or down) to the new value. The minimum capacitance should produce an initial dv/dt which is equal (but opposite in sign) to the dv/dt obtained by multiplying the di/dt in the inductor and the ESR of the capacitor:
C MIN =
An alternative to using a low value and high power current sense resistor is to reduce the sensed current by using a low cost current transformer and a diode. The current can then be sensed with a small-size, low cost SMT resistor. Using a transformer with one primary and 50 secondary turns reduces the worst-case resistor dissipation to a few mW. Another advantage of using this option is the separation of the current and voltage sensing, which makes the voltage sensing more accurate.
Power MOSFETs
(I
OMAX
- IOMIN x 0.8
)
RE (di / dt )
=
5 m x (2.0 V / 3.0 H )
(17 A - 1 A) x 0.8
Two external N-channel power MOSFETs must be selected for use with the ADP3157, one for the main switch, and an identical one for the synchronous switch. The main selection parameters for the power MOSFETs are the threshold voltage VGS(TH) and the on resistance RDS(ON). The minimum input voltage dictates whether standard threshold or logic-level threshold MOSFETs must be used. For VIN > 8 V, standard threshold MOSFETs (VGS(TH) < 4 V) may be used. If VIN is expected to drop below 8 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are strongly recommended. Only logic-level MOSFETs with VGS ratings higher than the absolute maximum of VCC should be used. The maximum output current IOMAX determines the RDS(ON) requirement for the two power MOSFETs. When the ADP3157 is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the average load current. For VIN = 5 V and VOUT = 2.8 V, the maximum duty ratio of the high side FET is: DMAXHF = (1-fMIN x tOFF) = (1 kHz-180 kHz x 3.0 s) = 46% The maximum duty ratio of the low side (synchronous rectifier) FET is: DMAXLF = 1 - DMAXHF = 54% The maximum rms current of the high side FET is: IRMSHS = [DMAXHF (ILVALLEY2 + ILPEAK2 + ILVALLEYILPEAK)/3]0.5 = 11.6 A rms
= 3840 F
In the above equation the value of di/dt is calculated as the smaller voltage across the inductor (i.e., VIN -VOUT rather than VOUT) divided by the maximum inductance inductor. The two parallel-connected 2200 F capacitors have a total capacitance of 4400 F, so the minimum capacitance requirement is met with ample margin.
RSENSE
The value of RSENSE is based on the required output current. The current comparator of the ADP3157 has a threshold range that extends from 0 mV to 125 mV (minimum). Note that the full 125 mV range cannot be used for the maximum specified nominal current, as headroom is needed for current ripple, and transients. The current comparator threshold sets the peak of the inductor current yielding a maximum output current, IOMAX, which equals the peak value less half of the peak-to-peak ripple current. Solving for RSENSE, allowing a 20% margin for overhead, and using the minimum current sense threshold of 125 mV, yields: RSENSE = (125 mV)/[1.2(IOMAX + IRPP/2)] = 5.0 m
-8-
REV. A
ADP3157
The maximum rms current of the low side FET is: IRMSLS = [DMAXLF (ILVALLEY2 + ILPEAK2 + ILVALLEYILPEAK)/3] = 12.5 A rms
0.5
All of the above-calculated junction temperatures are safely below the +175C maximum specified junction temperature of the selected FETs. The maximum operating junction temperature of the ADP3157 is calculated as follows: TJICMAX = TA + JA (IICVCC + PDR) where JA is the junction-to-ambient thermal impedance of the ADP3157 and PDR is the drive power. From the data sheet, JA is equal to 110C/W and IIC = 2.7 mA. PDR can be calculated as follows: PDR = (CRSS + CISS)VCC2 fMAX = 307 mW The result is: TJICMAX = +86C
CIN Selection and Input Current di/dt Reduction
The RDS(ON) for each FET can be derived from the allowable dissipation. If 5% of the maximum output power is allowed for FET dissipation, the total dissipation will be: PFETALL = 0.05 VOIOMAX = 1.7 W Allocating half of the total dissipation for the high side FET and half for the low side FET, the required minimum FET resistances will be: RDS(ON)HSF(MIN) = 0.85 W/(11.6 A)2 = 6 m RDS(ON)LSF(MIN) = 0.85 W/(12.5 A)2 = 5.5 m Note that there is a trade-off between converter efficiency and cost. Larger FETs reduce the conduction losses and allow higher efficiency, but increase the system cost. If efficiency is not a major concern, the International Rectifier IRL3803 is an economical choice for both the high side and low side positions. Those devices have an RDS(ON) of 6 m at VGS = 10 V and at +25C. The low side FET is turned on with at least 10 V. The high side FET, however, is turned on with only 12 V - 5 V = 7 V. The specified RDS(ON) at the expected highest FET junction temperature of +140C must be modified by: RDS(ON)MULT = 1.7 Using this multiplier, the expected RDS(ON) at +140C is 1.7 x 6 m = 10 m. The high side FET dissipation is: PDFETHS = IRMSHS2RDS(ON) + 0.5 VINILPEAKQGfMIN/IG ~ 2.3 W where the second term represents the turn-off loss of the FET. (In the second term, QGS is the gate charge to be removed from the gate for turn-off and IG is the gate current. From the data sheet, QGS is a 41 nC and the peak gate drive current provided by the ADP3157 is about 1 A.) The low side FET dissipation is: PDFETLS = IRMSLS RDS(ON) = 1.6 W (Note that there are no switching losses in the low side FET.) To maintain an acceptable MOSFET junction temperature, proper heat sinks should be used. The Thermalloy 6030 heat sink has a thermal impedance of 13C/W with convection cooling. With this heat sink, the junction-to-ambient thermal impedance of the chosen high side FET JAHS will be 13C/W (heat sink-to-ambient) + 2C/W (junction-to-case) + 0.5C/W (caseto-heat sink) = 15.5C/W. At full load, and at +50C ambient temperature, the junction temperature of the high side FET is: TJHSMAX = TA + JAHS PDFETHS = +86C The same heat sink may be used for the low side FET, e.g., the Thermalloy type 7141 ( = 20.3C/W). With this heat sink, the junction temperature of the low side FET is: TJLSMAX = TA + JALS PDFETLS = +82.5C
2
In continuous inductor-current mode, the source current of the high side MOSFET is a square wave with a duty ratio of VOUT/ VlN. To keep the input ripple voltage at a low value, one or more capacitors with low equivalent series resistance (ESR) and adequate ripple-current rating must be connected across the input terminals. The maximum rms current of the input bypass capacitors is: ICINRMS = 0.5 IOMAX = 8.5 A rms For an FA-type capacitor with 2700 F capacitance and 10 V voltage rating, the ESR is 34 m and the allowed ripple current at 100 kHz is 1.94 A. At +105C, at least four such capacitors must be connected in parallel to handle the calculated ripple current. At +50C ambient, however, a higher ripple current can be tolerated, so three capacitors in parallel are adequate. The ripple voltage across the three paralleled capacitors is: VCINRPL = IOMAX [ESRIN/3 +DMAXHF/(3 CIN fMIN )] = 100 mV p-p To further reduce the effect of the ripple voltage on the system supply voltage bus and to reduce the input-current di/dt to below the recommended maximum of 0.1 A/s, an additional small inductor (L > 1.7 H @ 10 A) should be inserted between the converter and the supply bus (see Figure 2).
Feedback Loop Compensation Design for Active Voltage Positioning
Optimized compensation of the ADP3157 allows the best possible containment of the peak-to-peak output voltage deviation. Any practical switching power converter is inherently limited by the inductor in its output current slew rate to a value much less than the slew rate of the load. Therefore, any sudden change of load current will initially flow through the output capacitors, and this will produce an output voltage deviation equal to the ESR of the output capacitor array times the load current change.
REV. A
-9-
ADP3157
To correctly implement active voltage positioning, the low frequency output impedance (i.e., the output resistance) of the converter should be made equal to the maximum ESR of the output capacitor array. This can be achieved by having a single pole roll-off of the voltage gain of the gm error amplifier, where the pole frequency coincides with the ESR zero of the output capacitor. A gain with single pole roll-off requires that the gm amplifier output pin be terminated by the parallel combination of a resistor and capacitor. The required resistor value can be calculated from the equation: Finally, the compensating capacitance is determined from the equality of the pole frequency of the error amplifier gain and the zero frequency of the impedance of the output capacitor:
CCOMP =
CO x ESR RtTOTAL
Trade-Offs Between DC Load Regulation and AC Load Regulation
RC =
where
RtTOTAL =
275 k x RtTOTAL 275 k - RtTOTAL
16.4 k x RCS x IOMAX VHI -VLO
and where the quantities 16.4 k and 275 k are characteristics of the ADP3157 and the value of the current sense resistor, RCS, has already been determined as above. Although a single termination resistor equal to RC would yield the proper voltage positioning gain, the dc biasing of that resistor would determine how the regulation band is centered (i.e., offset). Note that sometimes the specified regulation band is asymmetrical with respect to the nominal VID voltage. With the ADP3157, the offset is already considered as part of the design procedure--no special provision is required. To accomplish the dc biasing, it is simplest to use two resistors to terminate the gm amplifier output, with the lower resistor tied to ground and the upper resistor to the 12 V supply of the IC. The values of these resistors can be calculated using:
Casual observation of the circuit operation--e.g., with a voltmeter --would make it appear that the dc load regulation appears to be rather poor compared to a conventional regulator. This would be especially noticeable under very light or very heavy loads where the voltage is "positioned" near one of the extremes of the regulation window rather than near the nominal center value. It must be noted and understood that this low gain characteristic (i.e., loose dc load regulation) is inherently required to allow improved transient containment (i.e., to achieve tighter ac load regulation). That is, the dc load regulation is intentionally sacrificed (but kept within specification) in order to minimize the number of capacitors required to contain the load transients produced by the CPU.
LAYOUT AND COMPONENT PLACEMENT GUIDELINES
The following guidelines are recommended for optimal performance of a switching regulator in a PC system:
General Recommendations
1.
RUPPER = RC x
and
VDIV VOS
2.
For best results, a four-layer (minimum) PCB is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, a signal ground plane, power planes for both power ground and the input power (e.g., 5 V), and wide interconnection traces in the rest of the power delivery current paths. Each square unit of 1 ounce copper trace has a resistance of ~0.53 mW at room temperature. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. The power and ground planes should overlap each other as little as possible. It is generally easiest (although not necessary) to have the power and signal ground planes on the same PCB layer. The planes should be connected nearest to the first input capacitor where the input ground current flows from the converter back to the power source (e.g., 5 V).
RLOWER = RC x
VOS VDIV - VOS
3.
where VDIV is the resistor divider supply voltage (e.g., the recommended 12 V), and VOS is the offset voltage required on the amplifier to produce the desired offset at the output. VOS is calculated using Equation 2 below, where VOUT(OS) is the offset from the nominal VID-programmed value to the center of the specified regulation window for the output voltage. (Note this may be either positive or negative.) For clarification, that offset is given by:
1 VOUT (OS ) = (VHI +VLO )-VID 2
where VHI and VLO are the respective upper and lower limits allowed for regulation.
Rt Rt x 0.8 V + VOUT (OS ) TOTAL - 1.7 V TOTAL + 6 RCS IOMAX 1.36 k 275 k
VOS =
RC RtTOTAL
(2)
-10-
REV. A
ADP3157
4. If critical signal lines (including the voltage and current sense lines of the ADP3157) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. The PGND pin of the ADP3157 should connect first to a ceramic bypass capacitor (on the VCC pin) and then into the power ground plane using the shortest possible trace. However, the power ground plane should not extend under other signal components, including the ADP3157 itself. If necessary, follow the preceding guideline to use the signal plane as a shield between the power ground plane and the signal circuitry. The AGND pin of the ADP3157 should connect first to the timing capacitor (on the CT pin), and then into the signal ground plane. In cases where no signal ground plane can be used, short interconnections to other signal ground circuitry in the power converter should be used--the compensation capacitor being the next most critical. The output capacitors of the power converter should be connected to the signal ground plan even though power current flows in the ground of these capacitors. For this reason, it is advised to avoid critical ground connections (e.g., the signal circuitry of the power converter) in the signal ground plane between the input and output capacitors. It is also advised to keep the planar interconnection path short (i.e., have input and output capacitors close together). The output capacitors should also be connected as closely as possible to the load (or connector) that receives the power (e.g., a microprocessor core). If the load is distributed, the capacitors also should be distributed, and generally in proportion to where the load tends to be more dynamic. Absolutely avoid crossing any signal lines over the switching power path loop, described below. circulating current in the power converter, no longer finding a path for current through the channel of the lower FET, draws current through the inherent body-drain diode of the FET. The upper FET turns on, and the reverse recovery characteristic of the lower FET's body-drain diode prevents the drain voltage from being pulled high quickly. The upper FET then conducts very large current while it momentarily has a high voltage forced across it, which translates into added power dissipation in the upper FET. The Schottky diode minimizes this problem by carrying a majority of the circulating current when the lower FET is turned off, and by virtue of its essentially nonexistent reverse recovery time. 12. A small ferrite bead inductor placed in series with the drain of the lower FET can also help to reduce this previously described source of switching power loss. 13. Whenever a power dissipating component (e.g., a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are: improved current rating through the vias (if it is a current path), and improved thermal performance--especially if the vias extended to the opposite side of the PCB where a plane can more readily transfer the heat to the air. 14. The output power path, though not as critical as the switching power path, should also be routed to encompass a small area. The output power path is formed by the current path through the inductor, the current sensing resistor, the output capacitors, and back to the input capacitors. 15. For best EMI containment, the power ground plane should extend fully under all the power components except the output capacitors. These are: the input capacitors, the power MOSFETs and Schottky diode, the inductor, the current sense resistor and any snubbing elements that might be added to dampen ringing. Avoid extending the power ground under any other circuitry or signal lines, including the voltage and current sense lines.
Signal Circuitry
5.
6.
7.
8.
9.
Power Circuitry
10. The switching power path should be routed on the PCB to encompass the smallest possible area in order to minimize radiated switching noise energy (i.e., EMI). Failure to take proper precaution often results in EMI problems for the entire PC system as well as noise related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors, the two FETs, and the power Schottky diode if used, including all interconnecting PCB traces and planes. The use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause highenergy ringing, and it accommodates the high current demand with minimal voltage loss. 11. A power Schottky diode (1 ~ 2 A dc rating) placed from the lower FET's source (anode) to drain (cathode) will help to minimize switching power dissipation in the upper FET. In the absence of an effective Schottky diode, this dissipation occurs through the following sequence of switching events. The lower FET turns off in advance of the upper FET turning on (necessary to prevent cross-conduction). The REV. A
16. The output voltage is sensed and regulated between the AGND pin (which connects to the signal ground plane) and the SENSE- pin. The output current is sensed (as a voltage) and regulated between the SENSE- pin and the SENSE+ pin. In order to avoid differential mode noise pickup in those sensed signals, their loop areas should be small. Thus the SENSE- trace should be routed atop the signal ground plane, and the SENSE+ and SENSE- traces should be routed as a closely coupled pair (SENSE+ should be over the signal ground plane as well). 17. The SENSE+ and SENSE- traces should be Kelvin connected to the current sense resistor so that the additional voltage drop due to current flow on the PCB at the current sense resistor connections does not affect the sensed voltage. It is desirable to have the ADP3157 close to the output capacitor bank and not in the output power path, so that any voltage drop between the output capacitors and the AGND pin is minimized, and voltage regulation is not compromised.
-11-
ADP3157
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead SOIC (R-16A/SO-16)
C3502a-2-9/99
0.0196 (0.50) 0.0099 (0.25) 45 0.0500 (1.27) 0.0160 (0.41) 0.3937 (10.00) 0.3859 (9.80) 0.1574 (4.00) 0.1497 (3.80)
16 1 9 8
0.2440 (6.20) 0.2284 (5.80)
PIN 1
0.050 (1.27) BSC
0.0688 (1.75) 0.0532 (1.35)
0.0098 (0.25) 0.0040 (0.10)
8 0 0.0192 (0.49) SEATING 0.0099 (0.25) PLANE 0.0138 (0.35) 0.0075 (0.19)
-12-
REV. A
PRINTED IN U.S.A.

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